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Merge branch 'master' into jgrpp

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# Conflicts:
#	src/cargotype.h
#	src/core/CMakeLists.txt
#	src/core/span_type.hpp
#	src/fileio.cpp
#	src/fios.cpp
#	src/misc/endian_buffer.hpp
#	src/misc_gui.cpp
#	src/saveload/saveload.h
#	src/saveload/vehicle_sl.cpp
#	src/screenshot.cpp
#	src/settings.cpp
#	src/settings_internal.h
#	src/stdafx.h
#	src/string_func.h
#	src/strings.cpp
#	src/strings_func.h
#	src/strings_internal.h
This commit is contained in:
Jonathan G Rennison
2024-01-25 18:37:23 +00:00
parent c320a3fd7f 28ef5146ba
commit 822ecae85d
49 changed files with 127 additions and 472 deletions
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3
src/newgrf_spritegroup.cpp
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@@ -19,6 +19,7 @@
#include "scope.h"
#include "debug_settings.h"
#include "newgrf_engine.h"
#include <bit>
#include "safeguards.h"
@@ -212,7 +213,7 @@ static U EvalAdjustT(const DeterministicSpriteGroupAdjust &adjust, ScopeResolver
case DSGA_OP_STO: _temp_store.StoreValue((U)value, (S)last_value); return last_value;
case DSGA_OP_RST: return value;
case DSGA_OP_STOP: scope->StorePSA((U)value, (S)last_value); return last_value;
case DSGA_OP_ROR: return ROR<uint32_t>((U)last_value, (U)value & 0x1F); // mask 'value' to 5 bits, which should behave the same on all architectures.
case DSGA_OP_ROR: return std::rotr<uint32_t>((U)last_value, (U)value & 0x1F); // mask 'value' to 5 bits, which should behave the same on all architectures.
case DSGA_OP_SCMP: return ((S)last_value == (S)value) ? 1 : ((S)last_value < (S)value ? 0 : 2);
case DSGA_OP_UCMP: return ((U)last_value == (U)value) ? 1 : ((U)last_value < (U)value ? 0 : 2);
case DSGA_OP_SHL: return (uint32_t)(U)last_value << ((U)value & 0x1F); // Same behaviour as in ParamSet, mask 'value' to 5 bits, which should behave the same on all architectures.