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Add train is in slot conditional order

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This commit is contained in:
Jonathan G Rennison
2018-11-05 04:21:08 +00:00
parent c632539bb7
commit 83a063f51c
6 changed files with 51 additions and 6 deletions
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2
src/saveload/extended_ver_sl.cpp
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@@ -49,7 +49,7 @@ static const uint32 _sl_xv_slxi_chunk_version = 0; ///< current version
const SlxiSubChunkInfo _sl_xv_sub_chunk_infos[] = {
{ XSLFI_TRACE_RESTRICT, XSCF_NULL, 9, 9, "tracerestrict", NULL, NULL, "TRRM,TRRP,TRRS" },
{ XSLFI_TRACE_RESTRICT_OWNER, XSCF_NULL, 1, 1, "tracerestrict_owner", NULL, NULL, NULL },
{ XSLFI_TRACE_RESTRICT_ORDRCND, XSCF_NULL, 1, 1, "tracerestrict_order_cond", NULL, NULL, NULL },
{ XSLFI_TRACE_RESTRICT_ORDRCND, XSCF_NULL, 2, 2, "tracerestrict_order_cond", NULL, NULL, NULL },
{ XSLFI_TRACE_RESTRICT_STATUSCND,XSCF_NULL, 1, 1, "tracerestrict_status_cond", NULL, NULL, NULL },
{ XSLFI_PROG_SIGS, XSCF_NULL, 1, 1, "programmable_signals", NULL, NULL, "SPRG" },
{ XSLFI_ADJACENT_CROSSINGS, XSCF_NULL, 1, 1, "adjacent_crossings", NULL, NULL, NULL },