VarAction2: Replace divs of powers of 2 with shifts where possible
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@@ -5703,7 +5703,7 @@ static void NewSpriteGroup(ByteReader *buf)
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case DSGA_OP_XOR:
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if (adjust.and_mask <= 1) inference = prev_inference & (~VA2AIF_PREV_TERNARY);
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break;
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case DSGA_OP_MUL:
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case DSGA_OP_MUL: {
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if ((prev_inference & VA2AIF_ONE_OR_ZERO) && adjust.variable == 0x1A && adjust.shift_num == 0) {
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/* Found a ternary operator */
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adjust.operation = DSGA_OP_TERNARY;
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@@ -5739,8 +5739,17 @@ static void NewSpriteGroup(ByteReader *buf)
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}
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}
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inference = VA2AIF_PREV_TERNARY;
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break;
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}
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uint32 sign_bit = (1 << ((varsize * 8) - 1));
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if ((prev_inference & VA2AIF_PREV_MASK_ADJUST) && (prev_inference & VA2AIF_SIGNED_NON_NEGATIVE) && adjust.variable == 0x1A && adjust.shift_num == 0 && (adjust.and_mask & sign_bit) == 0) {
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/* Determine whether the result will be always non-negative */
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if (((uint64)group->adjusts[group->adjusts.size() - 2].and_mask) * ((uint64)adjust.and_mask) < ((uint64)sign_bit)) {
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inference |= VA2AIF_SIGNED_NON_NEGATIVE;
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}
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}
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break;
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}
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case DSGA_OP_SCMP:
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inference = VA2AIF_SIGNED_NON_NEGATIVE;
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/* Convert to UCMP if possible to make other analysis operations easier */
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@@ -5768,6 +5777,14 @@ static void NewSpriteGroup(ByteReader *buf)
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break;
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}
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}
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break;
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case DSGA_OP_SDIV:
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if ((prev_inference & VA2AIF_SIGNED_NON_NEGATIVE) && adjust.variable == 0x1A && adjust.shift_num == 0 && HasExactlyOneBit(adjust.and_mask)) {
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/* Convert to a shift */
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adjust.operation = DSGA_OP_SHR;
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adjust.and_mask = FindFirstBit(adjust.and_mask);
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inference |= VA2AIF_SIGNED_NON_NEGATIVE;
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}
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default:
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break;
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}
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